1. Field of the Invention
The present invention relates generally to a semiconductor device including an MOS capacitance and, more particularly, to a semiconductor device including an MOS capacitance improved so as to enhance accuracy of the MOS capacitance. The present invention also relates to a method of manufacturing such semiconductor devices.
2. Description of the Background Art
An MOS (Metal-Oxide-Semiconductor) capacitance is used for an A-D converter, a D-A converter and so on. FIGS. 10A to 10D show features of a method of manufacturing a conventional semiconductor device including an MOS capacitance shown in FIG. 11.
Referring to FIG. 10A, a P-type semiconductor substrate 1 is prepared, having a field oxide film 2 formed thereat. On semiconductor substrate 1, a resist film 3 is formed to mask a region except where a capacitance dope layer is to be formed.
Referring to FIGS. 10A and 10B, a capacitance dope layer 4 is formed by implanting phosphorus into the surface of semiconductor substrate 1 while using resist film 3 as a mask.
Referring to FIG. 10C, a P-well 5 is formed in the surface of semiconductor substrate 1 by selectively implanting boron into a region where a well needs to be formed, while using a resist film (not shown).
Referring to FIG. 10D, a doped polysilicon layer 6 is formed on semiconductor substrate 1, with an insulating film interposed, and a WSi layer 7 is formed thereon. Then, these layers are patterned to a shape of a gate electrode 8. Gate electrode 8 serves as one of upper/lower electrodes. A sidewall spacer 9 is formed on the sidewall of gate electrode 8. Next, an N.sup.+ diffusion layer 10 is formed by implanting N-type impurity ions into the surface of semiconductor substrate 1, while using gate electrode 8 and sidewall spacer 9 as a mask.
Thereafter, referring to FIG. 11, an interconnection 11 connecting to gate electrode 8 is formed on semiconductor substrate 1, and it connects N.sup.+ diffusion layer 10 to the other one of upper/lower electrodes 12.
FIG. 12 shows an arrangement of wells at the surface of a semiconductor substrate. The MOS capacitance shown in FIG. 11 is formed within P-well 5 shown in FIG. 12.
As described above, impurity diffusion layers (4, 10) of the conventional MOS capacitance are formed within a well. For instance, if impurity diffusion layers of an MOS capacitance are n.sup.+ -type, they are formed within a P-well. That is, P-well 5 is formed immediately under capacitance dope layer 4 as shown in FIG. 10D. In the MOS capacitance, applying voltage to an impurity diffusion layer and connecting a semiconductor substrate to ground produces electrostatic capacitance between an N.sup.+ layer and a P-well. This electrostatic capacitance is defined as parasitic capacitance. A problem is that larger value of the electrostatic capacitance decreases accuracy and limits usage of an MOS capacitance. Parasitic capacitance is represented by the following equations. ##EQU1## EQU .epsilon..sub.0 : vacuum permittivity EQU Ks: specific permittivity EQU W: width of depletion region ##EQU2## EQU NA: acceptor concentration EQU N.sub.D : donor concentration
if N.sub.D &gt;&gt;N.sub.A ##EQU3##
As is apparent from the above equations, the higher the concentration of a P-well, the greater the parasitic capacitance.